Multichannel Pulse Compression System for SAR Data Based on Xilinx's Virtex7 FPGA
Navneet Agrawal, Navneet
College of Technology & Engineering, MPUAT,Udaipur Rajasthan , INDIA, INDIA

The implementation of digital signal process of SAR data on Xilinx's Virtex7 FPGA system based on FPGA is an important method for embedded system. Pulse compression can be implemented in digital method. The realization of a multichannel pulse compression system by using all digital method has the characteristics of high reliability, strong anti-disturbance, good flexibility and convenient for application. In essence, pulse compression is a method of frequency spectrum expanding, and is used in matched filtering. It incarnates the matching level of filter and the expectant phase of received signal. A multichannel pulse compression system is designed using FFT IP core which can be reused in different periods of digital pulse compression, respectively performing FFT and IFFT calculation, so that the hardware consumption is saved significantly. This paper presents the logic programming of Multichannel Pulse Compression System based on Xilinx FPGA, and introduces the highspeed transmission module, the digital signal process module and the data buffer module in detail.

This design uses Xilinx's Virtex7 FPGA family, and achieves the pulse compression processing on AD collection down-converted signal by the method of frequency domain pulse pressure, meantime, it uses System Generator to perform the program's development in digital signal processing, which is the Xilinx's latest integrated development tools for digital processing system.

The main modules of pulse compression system includes the Rapid IO transmission interface, the Control- FPGA module, the RocketIO trans-mission interface, the digital signal processing FPGA module and PCI bus interface.
The Rapid IO transmission interface is used for highspeed data transmission between boards. As for this pulse compression system, itís mainly used to receive the data after AD sampling and digital down converter and transmit the data after pulse compression to the DSP board which makes further data processing. The Control-FPGA is used for data transmission and the system working state control. The data transmission includes PCI transmission, serial Rapid IO transmission and serial RocketIO transmission.
PCI bus interface is used for the transmission of control and status information between the upper machine and the Control-FPGA.
RocketIO transmission interface is used for the highspeed transmission between the Control-FPGA and the signal-processing FPGA.
The main tasks of the signal-processing FPGA include receiving the data after AD sampling and digital down converter, multichannel pulse compression process and transmitting the data after pulse compression to the DSP board. The signal-processing FPGA is the core of the pulse compression system. The following section mainly introduce the software structure of the signal-processing FPGA and the design of the key modules.